Design constraints in general, and specifically the Synopsys® Design Constraints (SDC), is a format used to specify a timing design intent for the design. The SDC format is based on the tool command language (Tel). The Synopsys® Design Compiler©, Integrated Circuit (IC) Compiler, Astro®, Jupiter XT™, and PrimeTime® tools, as well as third party electronic design automation (EDA) tools, all use the SDC description to synthesize and analyze the design. When a third party tool uses a SDC description it typically communicates with other tools through the SDC format as an interface, that is, it both receives a SDC format at its input and then provides an SDC format at its output.
For each functional or test mode to be modeled there is provided its respective SDC file that is used for the purpose of synthesis, static timing analysis, and implementation of the design. The designers of the design will typically attempt to optimize the design for each mode of operation despite of the conflicting requirements that may be presented by the designers. A design is considered completed once all the operation modes have been tested and validated. This is of course a time consuming and error-prone process.
There is therefore a need in the art to overcome the deficiencies of design constraint modeling in general, and in particular the use of a plurality of SDC files for such matters, and provide an alternative compatible solution that is time efficient and that provides the same level of coverage.